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CAT4109, CAV4109
Application Information
Power Dissipation
The power dissipation (P D ) of the CAT4109/CAV4109
can be calculated as follows:
Recommended Layout
Bypass capacitor C1 should be placed as close to the IC as
possible. RSET resistors should be directly connected to the
P D + V DD
I DD ) S V LEDN
I LEDN
GND pin of the device. For better thermal dissipation,
multiple via can be used to connect the GND pad to a large
where V LEDN is the voltage at the LED pin, and I LEDN is the
associated LED current. Combinations of high V LED
voltage or high ambient temperature can cause the
CAT4109/CAV4109 to enter thermal shutdown. In
applications where V LEDN is high, a resistor can be inserted
in series with the LED string to lower P D .
Thermal dissipation of the junction heat consists
primarily of two paths in series. The first path is the junction
to the case ( q JC ) thermal resistance which is defined by the
package style, and the second path is the case to ambient
( q CA ) thermal resistance, which is dependent on board
layout. The overall junction to ambient ( q JA ) thermal
resistance is equal to:
q JA + q JC ) q CA
For a given package style and board layout, the operating
junction temperature T J is a function of the power
dissipation P D , and the ambient temperature, resulting in the
following equation:
T J + T AMB ) P D ( q JC ) q CA ) + T AMB ) P D q JA
When mounted on a double ? sided printed circuit board
with two square inches of copper allocated for “heat
spreading”, the resulting q JA is about 74 ° C/W.
For example, at 60 ° C ambient temperature, the maximum
power dissipation is calculated as follow:
ground plane. It is also recommended to use large pads and
traces on the PCB wherever possible to spread out the heat.
The LEDs for this layout are driven from a separate supply
(VLED+), but they can also be driven from the same supply
connected to VDD.
Figure 15. Recommended Layout
P Dmax +
(T Jmax * T AMB )
q JA
+
(150 * 60)
74
+ 1.2 W
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